US 12,149,351 B2
Transport block mapping across slots
Mohammed Karmoose, San Diego, CA (US); and Jung Hyun Bae, San Diego, CA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 16, 2021, as Appl. No. 17/378,646.
Claims priority of provisional application 63/192,563, filed on May 24, 2021.
Claims priority of provisional application 63/153,943, filed on Feb. 25, 2021.
Claims priority of provisional application 63/138,382, filed on Jan. 15, 2021.
Claims priority of provisional application 63/134,584, filed on Jan. 6, 2021.
Claims priority of provisional application 63/062,423, filed on Aug. 6, 2020.
Prior Publication US 2022/0045789 A1, Feb. 10, 2022
Int. Cl. H04L 1/00 (2006.01); H04W 72/0446 (2023.01); H04W 72/1268 (2023.01); H04W 72/21 (2023.01)
CPC H04L 1/0071 (2013.01) [H04L 1/0068 (2013.01); H04W 72/0446 (2013.01); H04W 72/1268 (2013.01); H04W 72/21 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A transmit block processing chain circuitry for a transmitter device, comprising:
a code block determination circuit that determines a size of a code block that maps across at least one slot boundary between a first slot and a second slot of a wireless physical shared channel;
a rate matching circuit that rate matches bits of the code block to a number of bits available in a transport block that spans one or more slots of the wireless physical shared channel; and
an interleaver that interleaves a continuous output of the rate matching circuit independently for each slot, wherein an interleaver size is determined independently for each slot of the first slot and the second slot so that the code block that crosses the slot boundary between the first slot and the second slot is interleaved within the first slot and the second slot.