US 12,149,269 B2
Transmitter circuit and operation method thereof
Moon-Chul Choi, Suwon-si (KR); Sung-Yong Cho, Suwon-si (KR); Jaehyeok Baek, Suwon-si (KR); and Donggun An, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 24, 2023, as Appl. No. 18/189,521.
Claims priority of application No. 10-2022-0070998 (KR), filed on Jun. 10, 2022; and application No. 10-2022-0104214 (KR), filed on Aug. 19, 2022.
Prior Publication US 2023/0403040 A1, Dec. 14, 2023
Int. Cl. H04B 1/3827 (2015.01); H04B 1/04 (2006.01); H04B 7/005 (2006.01)
CPC H04B 1/0458 (2013.01) [H04B 1/0475 (2013.01); H04B 7/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transmitter circuit, comprising:
an encoder configured to receive an impedance code that is generated based on impedance calibration for impedance matching and to generate a delay compensation signal based on the impedance code;
a delay circuit configured to output delay data that are delayed by a delay value from input data, the delay value being determined based on the delay compensation signal; and
a feed-forward equalizer (FFE) configured to receive the input data and the delay data, and to equalize the input data based on a main coefficient used for the input data and an equalization coefficient used for the delay data to generate transmission data.