US 12,149,264 B2
Loop gain auto calibration using loop gain detector
Mao-Hsuan Chou, Hsinchu (TW); Ya-Tin Chang, Hsinchu (TW); Ruey-Bin Sheen, Taichung (TW); and Chih-Hsien Chang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jun. 6, 2023, as Appl. No. 18/329,801.
Application 18/329,801 is a continuation of application No. 17/752,385, filed on May 24, 2022, granted, now 11,689,214.
Application 17/752,385 is a continuation of application No. 17/111,585, filed on Dec. 4, 2020, granted, now 11,356,115, issued on Jun. 7, 2022.
Application 17/111,585 is a continuation of application No. 16/785,869, filed on Feb. 10, 2020, granted, now 10,868,562, issued on Dec. 15, 2020.
Prior Publication US 2023/0318617 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/20 (2006.01); G04F 10/00 (2006.01); H03L 7/087 (2006.01); H03M 3/00 (2006.01)
CPC H03M 3/382 (2013.01) [G04F 10/005 (2013.01); H03L 7/087 (2013.01); H03M 3/458 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a charge pump circuit configured to translate a clock skew into a voltage;
a sample and hold circuit configured to sample the voltage; and
a comparator configured to detect a loop gain associated with an input signal and based on the sampled voltage and to output a loop gain signal for adjustment of the input signal.