US 12,149,260 B2
Method and apparatus for decoding low-density parity-check (LDPC) code
Shiuan-Hao Kuo, New Taipei (TW); and Hung-Jen Huang, Taichung (TW)
Assigned to SILICON MOTION, INC., Zhubei (TW)
Filed by Silicon Motion, Inc., Zhubei (TW)
Filed on May 4, 2023, as Appl. No. 18/143,343.
Claims priority of application No. 202210715949.4 (CN), filed on Jun. 23, 2022.
Prior Publication US 2023/0421175 A1, Dec. 28, 2023
Int. Cl. H03M 13/11 (2006.01); H03M 13/37 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/1137 (2013.01) [H03M 13/1108 (2013.01); H03M 13/3746 (2013.01); H03M 13/6575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for decoding a Low-Density Parity-Check (LDPC) code, performed by an LDPC decoder comprising a variable-node calculation circuitry and a check-node calculation circuitry, the method comprising:
entering, by the LDPC decoder, a first-stage state when detecting a codeword has been stored in a static random access memory (SRAM), wherein the check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on the codeword and a parity check matrix to calculate a plurality of first syndromes in the first-stage state, and the codeword comprises user data and the LDPC code;
entering, by the LDPC decoder, a second-stage state when the first syndromes indicate that the codeword obtained in the first-stage state is incorrect, wherein the variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm according to the codeword, a plurality of first soft bits corresponding to the codeword, and the first syndromes to generate a plurality of variable nodes, and calculate a plurality of second soft bits for the variable nodes in the second-stage state, the check-node calculation circuitry is arranged operably to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate a plurality of second syndromes in the second-stage stage, each hard bit in the codeword is associated with at least one first soft bit to indicate a first likelihood of belief for this hard bit, and each variable node is associated with at least one second soft bit to indicate a second likelihood of belief for this variable; and
repeatedly entering, by the LDPC decoder, a third-stage state when the second syndromes indicate that the variable nodes generated in the second-stage state are incorrect until a decoding succeeds or a total number of iterations of the third-stage state exceeds a threshold, wherein the variable-node calculation circuitry is arranged operably to perform the bit flipping algorithm according to the variable nodes, the second soft bits corresponding to the variable nodes, and the second syndromes to generate a plurality of new variable nodes, and calculate a plurality of new second soft bits for the new variable nodes in each iteration of the third-stage state, and the check-node calculation circuitry is arranged operably to perform the modulo 2 multiplication on the new variable nodes and the parity check matrix to calculate a plurality of new second syndromes in each iteration of the third-stage stage.