US 12,149,259 B2
Single-cycle byte correcting and multi-byte detecting error code
Michael Brendan Sullivan, Austin, TX (US); Nirmal R. Saxena, Los Altos Hills, CA (US); and Stephen William Keckler, Austin, TX (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on Sep. 21, 2022, as Appl. No. 17/934,163.
Claims priority of provisional application 63/246,542, filed on Sep. 21, 2021.
Prior Publication US 2023/0089736 A1, Mar. 23, 2023
Int. Cl. G11C 29/00 (2006.01); H03M 13/00 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/098 (2013.01) [H03M 13/1515 (2013.01); H03M 13/1575 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising a memory array and peripheral circuits coupled to the memory array, the peripheral circuits comprising logic to decode a Reed-Solomon (RS) codeword read from the memory array in response to a signal received via a memory interface by:
calculating four syndrome symbols in accordance with the RS codeword, wherein each syndrome symbol comprises eight bits;
determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols;
comparing the three location bytes;
generating an output for the RS codeword based on the comparison of the three location bytes, wherein:
the output includes corrected data responsive to determining that the three location bytes match;
the output includes an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or
the output includes an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match; and
transmitting the output to a processor connected to the memory device via the memory interface.