CPC H03M 1/12 (2013.01) [H03M 1/00 (2013.01); G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 13/00 (2013.01); G06F 13/28 (2013.01); G06F 2213/28 (2013.01)] | 20 Claims |
1. A device comprising:
a plurality of control registers;
a plurality of result registers; and
an analog-to-digital converter (ADC), wherein the device is configured to:
in a single transfer state of the device,
initiate a first analog to digital conversion using the ADC based on content of a first control register of the plurality of control registers, and
store a first conversion result of the first analog to digital conversion in a first result register of the plurality of result registers; and
in a multiple transfer state of the device,
initiate a first set of multiple analog to digital conversions using the ADC based on content of a second control register of the plurality of control registers, and
store conversion results corresponding to the first set of multiple analog to digital conversions in a first set of multiple result registers of the plurality of result registers.
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