US 12,149,255 B2
Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable
Raja Prabhu J, Bangalore (IN); Ankit Seedher, Bangalore (IN); Srinath Sridharan, Bangalore (IN); Rakesh Kumar Gupta, Bangalore (IN); Nitesh Naidu, Bangalore (IN); Shivam Agrawal, Bangalore (IN); Jeevabharathi G, Bangalore (IN); and Purva Choudhary, Bangalore (IN)
Assigned to Shaoxing Yuanfang Semiconductor Co., Ltd., Zhejiang (CN)
Filed by Shaoxing Yuanfang Semiconductor Co., Ltd., Shaoxing (CN)
Filed on Jan. 10, 2024, as Appl. No. 18/408,614.
Application 18/408,614 is a division of application No. 17/806,735, filed on Jun. 14, 2022, granted, now 11,967,965.
Claims priority of application No. 202141050628 (IN), filed on Nov. 3, 2021.
Prior Publication US 2024/0154617 A1, May 9, 2024
Int. Cl. H03L 7/199 (2006.01); H03L 7/081 (2006.01); H03L 7/197 (2006.01); H03L 7/24 (2006.01)
CPC H03L 7/199 (2013.01) [H03L 7/0818 (2013.01); H03L 7/1976 (2013.01); H03L 7/24 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A clock generation circuit for generating a plurality of divided signals with pre-specified relative phase delays, said clock generation circuit comprising:
a plurality of phase-locked loops (PLLs), each generating a respective PLL output and a corresponding sub-set of divided signals of said plurality of divided signals,
wherein each divided signal of said plurality of divided signals is offset from a reference clock by at least said associated pre-specified phase delay,
wherein an external reset signal is designed to reset said plurality of PLLs, wherein said reset causes each PLL to be initialized and then attain a steady state, wherein all of said plurality of PLLs attain said steady state in a duration following said external reset signal,
wherein said reference clock is blocked in said duration.