US 12,149,253 B2
Period error correction in digital frequency locked loops
Janne Matias Pahkala, Oulu (FI)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 27, 2023, as Appl. No. 18/114,595.
Application 18/114,595 is a continuation of application No. 17/710,650, filed on Mar. 31, 2022, granted, now 11,595,049.
Prior Publication US 2023/0344433 A1, Oct. 26, 2023
Int. Cl. H03L 7/093 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01); G01S 7/03 (2006.01); H02M 3/02 (2006.01)
CPC H03L 7/093 (2013.01) [H03L 7/085 (2013.01); H03L 7/099 (2013.01); G01S 7/03 (2013.01); G01S 7/032 (2013.01); H02M 3/02 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A digital frequency locked loop (DFLL) device, comprising:
a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal;
a time-to-digital converter (TDC) coupled to the PFD;
a controller coupled to the TDC;
digitally controlled oscillator (DCO) controller coupled to the controller; and
a digitally controlled oscillator (DCO) coupled to the DCO controller, the DCO configured to provide the primary clock signal.