US 12,149,252 B2
Delta-sigma modulator with modified quantization error shaping
Luigi Grimaldi, Villach (AT); Dmytro Cherniak, Villach (AT); Fabio Padovan, Villach (AT); and Giovanni Boi, Villach (AT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Dec. 12, 2022, as Appl. No. 18/064,823.
Prior Publication US 2024/0195420 A1, Jun. 13, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/107 (2006.01); H03L 7/23 (2006.01)
CPC H03L 7/0818 (2013.01) [H03L 7/107 (2013.01); H03L 7/235 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital phase-locked loop (DPLL), comprising:
a delta-sigma modulator (DSM), including:
a delay component configured to perform noise shaping of a quantization error introduced by the DSM;
a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM; and
an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.