US 12,149,250 B2
Level shifting device and method
Denis Cottin, Crolles (FR); and Fabrice Romain, Voreppe (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Aug. 26, 2021, as Appl. No. 17/412,991.
Claims priority of application No. 2008826 (FR), filed on Aug. 31, 2020.
Prior Publication US 2022/0069811 A1, Mar. 3, 2022
Int. Cl. H03K 3/356 (2006.01); G09G 3/3225 (2016.01); H03K 19/0185 (2006.01)
CPC H03K 3/356113 (2013.01) [G09G 3/3225 (2013.01); H03K 3/35613 (2013.01); H03K 19/018521 (2013.01); G09G 2310/0289 (2013.01); G09G 2380/10 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a current mirror circuit including a first transistor coupled between a high supply potential node and a first intermediate node and a second transistor coupled between the high supply potential node and a second intermediate node, said second transistor having a control terminal coupled to a control terminal of the first transistor and the first intermediate node;
a current source coupled between the first intermediate node and a ground node;
a first capacitor coupled between the high supply potential node and the first intermediate node and configured to provide a first voltage;
a third transistor coupled between the second intermediate node and a low supply potential node, the third transistor being a diode connected transistor with a control terminal coupled to the second intermediate node;
a second capacitor coupled between the second intermediate node and the low supply potential node and configured to provide a second voltage;
a first output transistor of p-channel type and a second output transistor of n-channel type connected at an output node, wherein the first and second output transistors are electrically in series between the high supply potential node and the low supply potential node;
a first drive circuit configured to generate a first control signal applied to a control terminal of the first output transistor, said first control signal having a first gate-to-source voltage for turning on the first output transistor, where the first gate-to-source voltage has a high limit controlled by the first voltage; and
a second drive circuit configured to generate a second control signal applied to a control terminal of the second output transistor, said second control signal having a second gate-to-source voltage for turning on the second output transistor, where the second gate-to-source voltage has a high limit controlled by the second voltage.