US 12,149,247 B2
Frequency divider and memory device including the same
Jaewoo Lee, Seoul (KR); Yoo-Chang Sung, Hwaseong-si (KR); Jeongdon Ihm, Suwon-si (KR); Hojun Chang, Seoul (KR); and Jinseok Heo, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 14, 2022, as Appl. No. 17/932,023.
Claims priority of application No. 10-2022-0004912 (KR), filed on Jan. 12, 2022.
Prior Publication US 2023/0223941 A1, Jul. 13, 2023
Int. Cl. H03K 21/02 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); H03K 23/40 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC H03K 21/026 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); H03K 23/40 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A frequency divider comprising:
a frequency dividing core circuit comprising a plurality of transistors, and configured to generate at least one division clock signal based on a clock signal and an inverted clock signal;
a controller configured to generate a body bias control signal based on clock frequency information; and
an adaptive body bias (ABB) generator configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.