US 12,149,243 B2
Level shifting circuit manufacturing method
Yaqi Ma, Hsinchu (TW); Lei Pan, Hsinchu (TW); and JunKui Hu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Aug. 9, 2023, as Appl. No. 18/447,154.
Application 18/447,154 is a division of application No. 17/883,257, filed on Aug. 8, 2022, granted, now 11,831,310.
Application 17/883,257 is a continuation of application No. 17/384,409, filed on Jul. 23, 2021, granted, now 11,431,339, issued on Aug. 30, 2022.
Claims priority of application No. 202110787741.9 (CN), filed on Jul. 13, 2021.
Prior Publication US 2024/0022252 A1, Jan. 18, 2024
Int. Cl. H01L 27/092 (2006.01); G06F 30/392 (2020.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/018521 (2013.01) [G06F 30/392 (2020.01); H01L 27/092 (2013.01); H03K 3/037 (2013.01); H03K 3/35613 (2013.01); H03K 19/0185 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit (IC) structure, the method comprising:
forming first through fourth PMOS transistors in an n-well;
constructing a bias circuit comprising the first and second PMOS transistors;
constructing a level shifter comprising the third and fourth PMOS transistors;
building a first power distribution structure comprising electrical connections to each of the first and third PMOS transistors; and
building a second power distribution structure comprising electrical connections to each of the second and fourth PMOS transistors.