US 12,149,219 B2
Transconductor circuitry with adaptive biasing
Matthias Steiner, Premstätten (AT); and Nigel Greer, Hottot les Bagues (FR)
Assigned to AMS AG, Premstätten (AT)
Appl. No. 17/414,603
Filed by ams AG, Premstätten (AT)
PCT Filed Dec. 3, 2019, PCT No. PCT/EP2019/083477
§ 371(c)(1), (2) Date Jun. 16, 2021,
PCT Pub. No. WO2020/126475, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 18214610 (EP), filed on Dec. 20, 2018.
Prior Publication US 2022/0052660 A1, Feb. 17, 2022
Int. Cl. H03F 3/45 (2006.01)
CPC H03F 3/45475 (2013.01) [H03F 3/45179 (2013.01); H03F 3/45659 (2013.01); H03F 3/45708 (2013.01); H03F 2203/45061 (2013.01); H03F 2203/45078 (2013.01); H03F 2203/45288 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A transconductor circuitry with adaptive biasing, comprising:
a first input terminal to apply a first input signal,
a second input terminal to apply a second input signal,
a first current path including a first transistor and a first controllable current source to adjust a first biasing current of the first transistor in the first current path, the first transistor having a control node being coupled to the first input terminal,
a second current path including a second transistor and a second controllable current source to adjust a second biasing current of the second transistor in the second current path, the second transistor having a control node being coupled to the second input terminal,
a control circuit comprising an amplifier having an output node to generate a control signal to control the first and the second controllable current source in response to at least one of a first potential of a first node of the first current path and a second potential of a second node of the second current path,
wherein the first node is located between the first transistor and the first controllable current source, and the second node is located between the second transistor and the second controllable current source.