US 12,149,218 B2
Power amplifiers with adaptive bias for envelope tracking applications
Aleksey A. Lyalin, Moorpark, CA (US); Huiming Xu, Newbury Park, CA (US); Shayan Farahvash, Kensington, CA (US); and Georgios Palaskas, Portland, OR (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Apr. 28, 2023, as Appl. No. 18/308,939.
Application 18/308,939 is a continuation of application No. 17/934,340, filed on Sep. 22, 2022, granted, now 11,677,368.
Application 17/934,340 is a continuation of application No. 17/302,953, filed on May 17, 2021, granted, now 11,482,975, issued on Oct. 25, 2022.
Claims priority of provisional application 62/704,972, filed on Jun. 5, 2020.
Prior Publication US 2023/0291370 A1, Sep. 14, 2023
Int. Cl. H03F 3/24 (2006.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01); H04B 1/38 (2015.01)
CPC H03F 3/245 (2013.01) [H03F 1/0233 (2013.01); H04B 1/38 (2013.01); H03F 2200/105 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A mobile device comprising:
a transceiver configured to generate a radio frequency signal;
a power management system including an envelope tracker configured to control a voltage level of a power amplifier supply voltage based on an envelope of the radio frequency signal; and
a front end system including a power amplifier transistor configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage, and a current mirror configured to generate a bias voltage for the power amplifier transistor at a node, the current mirror including a first mirror transistor having a drain connected to the node, a second mirror transistor having a gate connected to a gate of the first minor transistor, a third mirror transistor having a source connected to the node, and a fourth mirror transistor having a gate connected to a gate of the third mirror transistor and a drain that receives the power amplifier supply voltage, the front end system further including a buffer including a first depletion-mode transistor having a gate connected to the node of the current mirror and a source connected to a gate of the power amplifier transistor.