US 12,149,208 B2
Electronic circuit and power amplifier comprising same
Sungku Yeo, Suwon-si (KR); Seunghun Wang, Daejeon (KR); Songcheol Hong, Daejeon (KR); Jaeseok Park, Suwon-si (KR); Jinseok Park, Daejeon (KR); and Chongmin Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and Korea Advanced Institute of Science and Technology, Daejeon (KR)
Appl. No. 17/430,173
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
PCT Filed Feb. 11, 2020, PCT No. PCT/KR2020/001903
§ 371(c)(1), (2) Date Aug. 11, 2021,
PCT Pub. No. WO2020/166938, PCT Pub. Date Aug. 20, 2020.
Claims priority of application No. 10-2019-0015701 (KR), filed on Feb. 11, 2019.
Prior Publication US 2022/0158588 A1, May 19, 2022
Int. Cl. H03F 1/14 (2006.01); H03F 1/02 (2006.01); H03F 3/21 (2006.01); H03F 3/72 (2006.01)
CPC H03F 1/0205 (2013.01) [H03F 3/211 (2013.01); H03F 3/72 (2013.01); H03F 2200/451 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
a first switch circuit, and
a second switch circuit,
wherein the first switch circuit comprises:
a first switch connected to a first port and a second switch connected to a second port, the first switch and the second switch being serially connected to each other;
a first parallel switch connected to a node between the first switch and the second switch;
a first shunt inductor connected to the node between the first switch and the second switch and configured to offset a parasitic capacitance component of the first parallel switch,
wherein the second switch circuit comprises:
a third switch connected to a third port and a fourth switch connected to a fourth port, the third switch and the fourth switch being serially connected to each other;
a second parallel switch connected to a node between the third switch and the fourth switch; and
a second shunt inductor connected to the node between the third switch and the fourth switch and configured to offset a parasitic capacitance component of the second parallel switch,
the second parallel switch being serially connected to the first parallel switch and the second shunt inductor being serially connected to the first shunt inductor.