US 12,149,207 B2
High voltage digital power amplifier
Ofir Degani, Nes-Ammin (IL); Assaf Ben-Bassat, Haifa (IL); Ashoke Ravi, Portland, OR (US); Ina Shternberg, Haifa (IL); and Naor Shay, Rehovot (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 18, 2021, as Appl. No. 17/323,189.
Prior Publication US 2022/0376657 A1, Nov. 24, 2022
Int. Cl. H03F 1/02 (2006.01); H03F 3/21 (2006.01)
CPC H03F 1/0205 (2013.01) [H03F 3/21 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A digital power amplifier circuit, comprising:
a plurality of p-type transistors, a first one of the plurality of p-type transistors having a gate configured to be coupled to a first signal that varies between a first voltage range defined by a first upper voltage level and a first lower voltage level;
a plurality of n-type transistors, a first one of the plurality of n-type transistors having a gate configured to be coupled to a second signal that varies between a second voltage range defined by a second upper voltage level and a second lower voltage level; and
a pair of transistors coupled to a gate of a second one of the plurality of p-type transistors and to a second one of the plurality of n-type transistors to form a capacitive divider between (i) the pair of transistors, and (ii) the second one of the plurality of p-type transistors and the second one of the plurality of n-type transistors thereby defining a feedback capacitive ratio,
wherein an output of the digital power amplifier circuit is configured to generate an output signal in accordance with the feedback capacitive ratio such that the output signal varies between a third voltage range defined by the first upper voltage level of the first signal and the second lower voltage level of the second signal.