	US 12,149,184 B1
	Multi-mode control method for grid-connected inverter
Xing Zhang, Hefei (CN); Feng Han, Hefei (CN); Xiangdui Zhan, Hefei (CN); Yu Xiao, Hefei (CN); and Xinxin Fu, Hefei (CN)
Assigned to HEFEI UNIVERSITY OF TECHNOLOGY, Hefei (CN)
Filed by HEFEI UNIVERSITY OF TECHNOLOGY, Hefei (CN)
Filed on Jun. 26, 2024, as Appl. No. 18/754,219.
Claims priority of application No. 202311534477.3 (CN), filed on Nov. 17, 2023.
Int. Cl. H02M 7/5387 (2007.01); H02J 3/18 (2006.01); H02J 3/38 (2006.01); H02M 7/5395 (2006.01)

CPC H02M 7/53871 (2013.01) [H02J 3/1807 (2013.01); H02J 3/381 (2013.01); H02M 7/5395 (2013.01)]

5 Claims

1. A multi-mode control method for a grid-connected inverter, wherein a topology of the grid-connected inverter using the multi-mode control method comprises a direct current (DC) side power supply, a three-phase full-bridge inverter circuit, an LC filter, a grid impedor, and a three-phase power grid; the three-phase full-bridge inverter circuit, the LC filter, and the grid impedor are sequentially connected in series and then connected to the three-phase power grid; and the LC filter comprises a filtering inductor, a filtering capacitor, and a damping resistor; and

the multi-mode control method comprises the following steps:

step 1, sampling three-phase voltages u_pcca, u_pccb, and u_pcccof the filtering capacitor and three-phase currents i_ga, i_gb, and i_gcof the filtering inductor;

step 2, allowing the grid-connected inverter to operate in an added-damping-free current control mode;

step 3, continuously calculating an effective value V_HarRms1of a series compensation voltage harmonic of the filtering capacitor and an effective value V_HarRms2of a weak grid voltage harmonic of the filtering capacitor;

step 4, initiating a system short-circuit ratio (SCR) estimation method as follows:

step 4.1, defining a switching boundary of a system SCR as S_m, and defining a limit for the effective value of the weak grid voltage harmonic of the filtering capacitor as V_Limit2; defining a proportional coefficient of a current control proportional-integral (PI) controller in the added-damping-free current control mode as k_{p_cc}; and defining a switching boundary of the proportional coefficient of the current control PI controller in the added-damping-free current control mode as k_{p_cc_m}, wherein specifically, the proportional coefficient of the current control PI controller refers to a proportional coefficient that makes V_HarRms2=V_Limit2when the system SCR=S_m;

step 4.2, defining an initial value of k_{p_cc}as k_{p_cc_0}, and continuously increasing k_{p_cc}to excite the voltage harmonic of the filtering capacitor; and stopping increasing k_{p_cc}when V_HarRms2=V_Limit2, and recording k_{p_cc}as a measured value k_{p_cc_n}of the proportional coefficient of the current control PI controller in the added-damping-free current control mode;

step 4.3, determining that:

a current system SCR<S_mwhen k_{p_cc_n}<k_{p_cc_m};

the current system SCR=S_mwhen k_{p_cc_n}=k_{p_cc_m}; and

the current system SCR>S_mwhen k_{p_cc_n}>k_{p_cc_m}; and

step 4.4, restoring the proportional coefficient k_{p_cc}of the current control PI controller in the added-damping-free current control mode to the initial value k_{p_cc_0};

step 5, defining a system series compensation degree as K_c, and initiating a system series compensation degree K_cestimation method as follows:

step 5.1, defining a switching boundary of the system series compensation degree as C_m; defining a limit for the effective value of the series compensation voltage harmonic of the filtering capacitor as V_Limit1, and defining a bandwidth of a phase-locked loop in the added-damping-free current control mode as f_{bw_PLL}; and defining a switching boundary of the bandwidth of the phase-locked loop in the added-damping-free current control mode as f_{bw_PLL_m}, wherein the bandwidth of the phase-locked loop refers to a bandwidth that makes V_HarRms1=V_Limit1when the system series compensation degree K_c=C_m;

step 5.2, defining an initial value of f_{bw_PLL}as f_{bw_PLL_0}, and continuously increasing f_{bw_PLL}to excite the voltage harmonic of the filtering capacitor; and stopping increasing f_{bw_PLL}when V_HarRms1=V_Limit1, and recording f_{bw_PLL}as a measured value f_{bw_PLL_n}of the bandwidth of the phase-locked loop in the added-damping-free current control mode;

step 5.3, determining that:

a current system series compensation degree K_c>C_mwhen f_{bw_PLL_n}<f_{bw_PLL_m};

the current system series compensation degree Ke-C_mwhen f_{bw_PLL_n}=f_{bw_PLL_m}; and

the current system series compensation degree K_c<C_mwhen f_{bw_PLL_n}>f_{bw_PLL_m}; and

step 5.4, restoring the bandwidth f_{bw_PLL}of the phase-locked loop in the added-damping-free current control mode to the initial value f_{bw_PLL_0};

step 6, performing the following operations based on the system SCR:

when SCR≤S_m: switching the grid-connected inverter to a voltage control mode, and ending a present control process; and

when SCR>S_m: proceeding to step 7; and

step 7, performing the following operations based on the system series compensation degree K_c:

when K_c>C_m: switching the grid-connected inverter to an added-damping-based current control mode, and ending the present control process; and

when K_c≤C_m: maintaining the grid-connected inverter to operate in the added-damping-free current control mode, and ending the present control process.