US 12,148,853 B2
Germanium-based sensor with junction-gate field effect transistor and method of fabricating thereof
Jhy-Jyi Sze, Hsin-Chu (TW); Sin-Yi Jiang, Hsinchu (TW); Yi-Shin Chu, Hsinchu (TW); Yin-Kai Liao, Taipei (TW); Hsiang-Lin Chen, Hsinchu (TW); and Kuan-Chieh Huang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 29, 2023, as Appl. No. 18/523,523.
Application 18/523,523 is a continuation of application No. 18/151,828, filed on Jan. 9, 2023, granted, now 11,855,237.
Application 18/151,828 is a continuation of application No. 17/383,687, filed on Jul. 23, 2021, granted, now 11,600,737, issued on Mar. 7, 2023.
Claims priority of provisional application 63/161,687, filed on Mar. 16, 2021.
Prior Publication US 2024/0105877 A1, Mar. 28, 2024
Int. Cl. H01L 31/112 (2006.01); H01L 27/146 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/808 (2006.01); H01L 31/18 (2006.01)
CPC H01L 31/1129 (2013.01) [H01L 27/14679 (2013.01); H01L 29/66893 (2013.01); H01L 29/808 (2013.01); H01L 31/112 (2013.01); H01L 31/1804 (2013.01); H01L 31/1864 (2013.01); H01L 29/1066 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a photosensitive device, the method comprising:
forming a patterning layer over a substrate of a first semiconductor material;
etching the substrate using the patterning layer as an etch mask, wherein the etching forms a trench having a bottom and sidewalls formed by the substrate;
forming a first semiconductor layer of the first semiconductor material that partially fills the trench and lines the bottom and the sidewalls of the trench;
forming a second semiconductor layer of a second semiconductor material that fills a remainder of the trench and is over the first semiconductor layer;
after forming a dielectric layer over the second semiconductor layer, forming a first doped region, a second doped region, a third doped region, a fourth doped region, a fifth doped region, and a sixth doped region in the second semiconductor layer, wherein:
the first doped region is between the second doped region and the third doped region, the fifth doped region overlaps the first doped region and the second doped region, the sixth doped region overlaps the first doped region and the third doped region, and the fourth doped region is between the fifth doped region and the sixth doped region,
the first doped region, the fifth doped region, and the sixth doped region include a first type dopant, and
the second doped region, the third doped region, and the fourth doped region include a second type dopant; and
forming a third semiconductor layer of a third semiconductor material and a fourth semiconductor layer of the third semiconductor material over the fourth doped region, wherein the third semiconductor layer and the fourth semiconductor layer include the second type dopant, the third semiconductor layer and the fourth semiconductor layer are between the fifth doped region and the sixth doped region, and the third semiconductor layer and the fourth semiconductor layer are disposed in the dielectric layer.