US 12,148,842 B2
Semiconductor substrate and display device
Masataka Ikeda, Tokyo (JP); Hirotaka Hayashi, Tokyo (JP); and Hitoshi Tanaka, Tokyo (JP)
Assigned to JAPAN DISPLAY INC., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Mar. 10, 2023, as Appl. No. 18/181,572.
Application 18/181,572 is a continuation of application No. 16/779,680, filed on Feb. 3, 2020, granted, now 11,626,520.
Claims priority of application No. 2019-019792 (JP), filed on Feb. 6, 2019; and application No. 2019-119960 (JP), filed on Jun. 27, 2019.
Prior Publication US 2023/0215957 A1, Jul. 6, 2023
Int. Cl. H01L 29/786 (2006.01); G02F 1/167 (2019.01); G02F 1/16766 (2019.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01)
CPC H01L 29/78696 (2013.01) [G02F 1/167 (2013.01); G02F 1/16766 (2019.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 28/60 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor substrate comprising:
a gate line extending in a first direction;
a source line extending in a second direction intersecting the first direction;
a pixel electrode;
a first semiconductor layer connected to the source line and the pixel electrode; and
a second semiconductor layer connected to the source line and the pixel electrode,
wherein
the first semiconductor layer and the second semiconductor layer wholly overlap the gate line, and
the first semiconductor layer and the second semiconductor layer extend in the first direction and are arranged to be spaced apart in the second direction.