US 12,148,838 B2
Active via
Douglas W. Barlage, Edmonton (CA); and Lhing Gem Shoute, Edmonton (CA)
Assigned to ZINITE CORPORATION, Vancouver (CA)
Filed by ZINITE CORPORATION, Vancouver (CA)
Filed on Jan. 3, 2024, as Appl. No. 18/403,268.
Application 18/403,268 is a continuation of application No. PCT/IB2022/056397, filed on Jul. 11, 2022.
Claims priority of provisional application 63/221,292, filed on Jul. 13, 2021.
Prior Publication US 2024/0136330 A1, Apr. 25, 2024
Int. Cl. H01L 29/786 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 23/552 (2013.01); H01L 25/0657 (2013.01); H01L 25/16 (2013.01); H01L 27/0248 (2013.01); H01L 29/66969 (2013.01); H01L 29/78603 (2013.01); H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H01L 2225/06541 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for forming an active via in a semiconductor die, comprising:
forming a via through the die, the via having a first end and a second end;
forming a source contact at the first end of the via;
forming a source-channel interfacial member within the via and over the source contact, wherein the source-channel interfacial member includes a semiconductor material, and wherein the source-channel interfacial member is formed by oxidizing the source contact;
forming a semiconductor layer within the via and over the source-channel interfacial member;
forming a gate dielectric within the via and over the semiconductor layer;
forming a gate contact within the via and over the gate dielectric;
forming a gate electrode at the second end of the via and in contact with the gate contact to electrically connect the gate contact to a control circuit; and
forming a drain contact at the second end of the via, the drain contact in contact with the semiconductor layer.