US 12,148,837 B2
Semiconductor devices
Yi-Bo Liao, Hsinchu (TW); Yu-Xuan Huang, Hsinchu (TW); Pei-Yu Wang, Hsinchu (TW); Cheng-Ting Chung, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Hou-Yu Chen, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,357.
Application 18/357,357 is a continuation of application No. 17/671,156, filed on Feb. 14, 2022, granted, now 11,757,042.
Application 17/671,156 is a continuation of application No. 16/998,576, filed on Aug. 20, 2020, granted, now 11,251,308, issued on Feb. 15, 2022.
Claims priority of provisional application 63/016,520, filed on Apr. 28, 2020.
Prior Publication US 2023/0369504 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 23/5286 (2013.01); H01L 29/0673 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/7848 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first dielectric layer;
a channel region over the first dielectric layer;
a gate structure over the channel region;
a source/drain region adjacent the gate structure;
a second dielectric layer over the source/drain region; and
a conductive via extending through the second dielectric layer and the first dielectric layer, a top surface of the conductive via being coplanar with a top surface of the gate structure.