US 12,148,836 B2
Gate-all-around structure and methods of forming the same
Pei-Hsun Wang, Hsinchu (TW); Chih-Hao Wang, Hsinchu County (TW); and Chun-Hsiung Lin, Hsinchu (TW)
Assigned to Parabellum Strategic Opportunities Fund LLC, Wilmington, DE (US)
Filed by Parabellum Strategic Opportunities Fund LLC, Wilmington, DE (US)
Filed on Apr. 24, 2023, as Appl. No. 18/305,584.
Application 18/305,584 is a continuation of application No. 17/175,816, filed on Feb. 15, 2021, granted, now 11,637,207.
Application 17/175,816 is a continuation of application No. 16/511,176, filed on Jul. 15, 2019, granted, now 10,923,598, issued on Feb. 16, 2021.
Claims priority of provisional application 62/771,627, filed on Nov. 27, 2018.
Prior Publication US 2023/0261114 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a fin protruding from a substrate and disposed between portions of an isolation structure;
a semiconductor layer over the fin;
a gate dielectric wrapping around the semiconductor layer;
a gate electrode wrapping around the gate dielectric disposed on the semiconductor layer;
a source/drain feature interfacing with the semiconductor layer; and
a dielectric inner spacer having first portions contacting side surfaces of the source/drain feature and second portions contacting top and bottom surfaces of the source/drain feature; and
an etch stop layer over and in direct contact with the dielectric inner spacer.