US 12,148,834 B2
FinFET structure having a gate contact above a metal gate and straddling the boundary of an active region
Xinfang Liu, Shenzhen (CN); Miao Xu, Shanghai (CN); and Yanxiang Liu, Shenzhen (CN)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Apr. 9, 2021, as Appl. No. 17/226,563.
Application 17/226,563 is a continuation of application No. PCT/CN2018/109671, filed on Oct. 10, 2018.
Prior Publication US 2021/0257494 A1, Aug. 19, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 21/28123 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/4983 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/4966 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A field-effect transistor structure comprising:
a semiconductor substrate;
a source located in an active region above the semiconductor substrate;
a drain located in the active region above the semiconductor substrate;
a metal gate having a first bottom end located above the active region, wherein the metal gate has a first side and a second side;
a first metal trench associated with the source, wherein the first metal trench is located on the first side of the metal gate and has a second bottom end above a first top end face of the source in the active region;
a second metal trench associated with the drain, wherein the second metal trench is located on the second side of the metal gate and has a third bottom end above a second top end face of the drain in the active region, wherein the second bottom end of the first metal trench and the third bottom end of the second metal trench are at a same height of the first bottom end of the metal gate, and wherein the first top end face of the source and the second top end face of the drain are at a same height of the first bottom end of the metal gate;
an etching-stop layer overlaid on the first metal trench and the second metal trench;
a gate contact located above the metal gate and is at least partially above the active region;
a spacer located between the first metal trench and the metal gate and between the second metal trench and the metal gate, wherein a third top end face of the spacer and a fourth top end face of the etching-stop layer are at a same height;
a metal belt located above the gate contact and connected to the metal gate using the gate contact wherein the metal belt is located above the spacer and the etching-stop layer, wherein the etching-stop layer is configured to isolate the metal belt from the first metal trench and isolate the metal belt from the second metal trench; and
a semiconductor fin located above the semiconductor substrate, wherein the semiconductor fin and the metal gate are arranged in a cross manner, and wherein the semiconductor fin passes through the metal gate, wherein the gate contact extends from outside the active region to above the active region, and wherein a first part of the gate contact is outside the active region and a second part of the gate contact is in the active region, and wherein the second part that is in the active region does not cross the semiconductor fin.
 
19. A field-effect transistor structure comprising:
a semiconductor substrate;
a source located in an active region above the semiconductor substrate;
a drain located in the active region above the semiconductor substrate;
a metal gate having a first bottom end located above the active region, wherein the metal gate has a first side and a second side;
a first metal trench associated with the source, wherein the first metal trench is located on the first side of the metal gate and has a second bottom end above a first top end face of the source in the active region;
a second metal trench associated with the drain, wherein the second metal trench is located on the second side of the metal gate and has a third bottom end above a second top end face of the drain in the active region, wherein the second bottom end of the first metal trench and the third bottom end of the second metal trench are at a same height of the first bottom end of the metal gate, and wherein the first top end face of the source and the second top end face of the drain are at a same height of the first bottom end of the metal gate;
an etching-stop layer overlaid on the first metal trench and the second metal trench;
a gate contact located above the metal gate and is at least partially above the active region; and
a semiconductor fin located above the semiconductor substrate, wherein the semiconductor fin and the metal gate are arranged in a cross manner, and wherein the semiconductor fin passes through the metal gate, wherein the gate contact extends from outside the active region to above the active region, and wherein a first part of the gate contact is outside the active region and a second part of the gate contact is in the active region, and wherein the second part that is in the active region does not cross the semiconductor fin.