| CPC H01L 29/785 (2013.01) [H01L 29/41791 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 21/823425 (2013.01); H01L 21/823468 (2013.01); H01L 21/823864 (2013.01); H01L 29/165 (2013.01); H01L 29/7848 (2013.01)] | 20 Claims |
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1. A method, comprising:
forming a gate stack over a fin of a substrate;
sequentially depositing a first dielectric layer, a second dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than a dielectric constant of the first dielectric layer;
polishing the first dielectric layer, the second dielectric layer, and the filling dielectric to expose a top surface of a gate mask of the gate stack;
etching back the first dielectric layer, the second dielectric layer, and the filling dielectric such that top surfaces of the first dielectric layer, the second dielectric layer, and the filling dielectric are lower than a gate electrode of the gate stack;
forming a dielectric cap over the first and second dielectric layers and the filling dielectric;
etching the dielectric cap, the first and second dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack, wherein each of the gate spacers comprises remaining portions of the dielectric cap and the first and second dielectric layers; and
forming an epitaxy source/drain structure over the fin.
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