US 12,148,830 B2
Method and device for boosting performance of FinFETs via strained spacer
Kai-Chieh Yang, Hsinchu (TW); Wei Ju Lee, Kaohsiung (TW); Li-Yang Chuang, Hsinchu (TW); Pei-Yu Wang, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 26, 2023, as Appl. No. 18/324,405.
Application 18/324,405 is a continuation of application No. 17/216,241, filed on Mar. 29, 2021, granted, now 11,664,451.
Application 17/216,241 is a continuation of application No. 16/441,080, filed on Jun. 14, 2019, granted, now 10,964,816, issued on Mar. 30, 2021.
Claims priority of provisional application 62/737,238, filed on Sep. 27, 2018.
Prior Publication US 2023/0299200 A1, Sep. 21, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01)
CPC H01L 29/7843 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
an isolation structure;
a first dielectric fin, a second dielectric fin, and a third dielectric fin extending parallel to one another and vertically into the isolation structure;
a first semiconductor fin disposed in the isolation structure and between the first dielectric fin and the second dielectric fin;
a second semiconductor fin disposed in the isolation structure and between the second dielectric fin and the third dielectric fin;
a first source/drain feature disposed on the first semiconductor fin and partially in contact with the first dielectric fin and the second dielectric fin; and
a second source/drain feature disposed on the second semiconductor fin and spaced apart from the second dielectric fin and the third dielectric fin.