US 12,148,828 B2
Semiconductor device and manufacturing method thereof
Georgios Vellianitis, Heverlee (BE); Chun-Chieh Lu, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); and Mauricio Manfrini, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Dec. 16, 2020, as Appl. No. 17/123,982.
Claims priority of provisional application 63/040,681, filed on Jun. 18, 2020.
Prior Publication US 2021/0399136 A1, Dec. 23, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 21/383 (2006.01); H01L 21/447 (2006.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/78391 (2014.09) [H01L 21/383 (2013.01); H01L 21/447 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 27/1207 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate layer;
an aluminum oxide semiconductor layer comprising aluminum oxide;
a ferroelectric gate dielectric layer comprising HfxZn1-xO2 disposed between the gate layer and the aluminum oxide semiconductor layer, wherein x is greater than or equal to 0.1 and less than or equal to 0.9;
an interfacial layer located between the aluminum oxide semiconductor layer and the ferroelectric gate dielectric layer, the interfacial layer having a thickness greater than 0.1 nanometers and less than 1 nanometers and being less than 10% of a thickness of the ferroelectric gate dielectric layer, the interfacial layer comprising elements of both the aluminum oxide semiconductor layer and the ferroelectric gate dielectric layer in varying stoichiometric ratios over a thickness of the interfacial layer between the aluminum oxide semiconductor layer and the gate dielectric ferroelectric layer;
wherein the interfacial layer is formed by performing a pressurized treatment while an aluminum oxide semiconductor material layer and a ferroelectric material layer are in place over the gate layer, whereby the pressurized treatment transforms the aluminum oxide semiconductor material layer into the aluminum oxide semiconductor layer such that the aluminum oxide semiconductor layer has an electron doping value that is less than that of the aluminum oxide semiconductor material layer and that ranges from 1E17 cm-3 to 1E19 cm-3, and whereby the pressurized treatment also transforms the ferroelectric material layer into the ferroelectric gate dielectric layer such that the ferroelectric gate dielectric layer is a crystalline ferroelectric layer; and
a source terminal and a drain terminal disposed on the aluminum oxide semiconductor layer and spaced apart from one another by a distance, the source terminal and drain terminal each including a metallic core, a seed layer arranged along outer sidewalls of the metal core and separating the metallic core from the aluminum oxide semiconductor layer, and a barrier layer arranged along outer sidewalls of the seed layer and separating the seed layer from the aluminum oxide semiconductor layer.