US 12,148,827 B2
Method of making an integrated circuit with drain well having multiple zones
Zheng Long Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Aug. 10, 2022, as Appl. No. 17/884,872.
Application 17/884,872 is a division of application No. 17/165,126, filed on Feb. 2, 2021, granted, now 11,837,659.
Claims priority of application No. 202011082905.X (CN), filed on Oct. 12, 2020.
Prior Publication US 2022/0384646 A1, Dec. 1, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7833 (2013.01) [H01L 29/66553 (2013.01); H01L 29/66689 (2013.01); H01L 29/7817 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of making an integrated circuit, comprising:
forming a drift region in a substrate, the drift region having a first dopant type;
forming a drain well in the drift region, the drain well having the first dopant type, the drain well comprising a first zone with a first concentration of the first dopant and a second zone having a second concentration of the first dopant different from the first concentration of the first dopant;
forming a source well in the substrate, the source well having a second dopant type opposite from the first dopant type, the source well directly contacting the drift region in the substrate;
forming a gate electrode over a top surface of the substrate over the drift region and the source well, and being laterally separated from the drain well;
forming a drain low-density doped (LDD) region in the second zone of the drain well.