US 12,148,823 B2
Double-channel HEMT device and manufacturing method thereof
Ferdinando Iucolano, Gravina di Catania (IT); and Alessandro Chini, Modena (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Oct. 31, 2022, as Appl. No. 17/977,971.
Application 17/977,971 is a continuation of application No. 17/115,459, filed on Dec. 8, 2020, granted, now 11,489,068.
Application 17/115,459 is a continuation of application No. 16/431,642, filed on Jun. 4, 2019, granted, now 10,892,357, issued on Jan. 12, 2021.
Application 16/431,642 is a continuation of application No. 15/393,945, filed on Dec. 29, 2016, granted, now 10,381,470, issued on Aug. 13, 2019.
Claims priority of application No. 16425047 (EP), filed on May 30, 2016.
Prior Publication US 2023/0047815 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7787 (2013.01) [H01L 21/02458 (2013.01); H01L 21/0254 (2013.01); H01L 29/0657 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/7786 (2013.01); H01L 29/41766 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A structure, comprising:
a first semiconductor layer over a substrate;
a second semiconductor layer over the first semiconductor layer;
a third semiconductor layer over the second semiconductor layer, the third semiconductor layer including a first portion and a second portion;
a first dielectric layer over the second semiconductor layer and the third semiconductor layer and in vertical contact with the second semiconductor layer;
a drain region extending through the first dielectric layer and the second semiconductor layer;
a source region extending through the first dielectric layer and the second semiconductor layer; and
a gate structure extending through the first dielectric layer and the second semiconductor layer and in contact with the first semiconductor layer, the first portion of the third semiconductor layer positioned between the drain region and a first side of the gate structure, the first side of the gate structure spaced apart from the first portion of the third semiconductor layer by the first dielectric layer, the second portion of the third semiconductor layer positioned between the source region and a second side of the gate structure, the second side of the gate structure in contact with the second portion of the third semiconductor layer, the second side opposite to the first side of the gate structure.