US 12,148,820 B2
Transistors with source-connected field plates
Congyong Zhu, Gilbert, AZ (US); Bernhard Grote, Phoenix, AZ (US); and Bruce McRae Green, Gilbert, AZ (US)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Dec. 20, 2021, as Appl. No. 17/645,286.
Prior Publication US 2023/0197839 A1, Jun. 22, 2023
Int. Cl. H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/778 (2013.01) [H01L 29/2003 (2013.01); H01L 29/66462 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device comprising:
receiving a semiconductor substrate having: a channel region suitable for use as a transistor channel; and a top surface dielectric in direct contact with a top surface of the substrate that overlies the channel region;
simultaneously forming first and second apertures in the top surface dielectric above the channel region, wherein:
the first aperture is disposed at a location between a first end of the channel region and a second end of the channel region;
the second aperture is separated from the first aperture and disposed at a location between the first aperture and the second end of the channel region;
forming a control electrode within the first aperture that directly contacts the top surface of the substrate;
depositing a field plate dielectric that directly contacts the top surface above the channel region in the second aperture; and
forming a field plate electrode in the second aperture that is separated from the top surface of the substrate by the field plate dielectric.