US 12,148,813 B2
Field-effect transistor device with gate spacer structure
Wei-Che Hsieh, New Taipei (TW); and Chunyao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 12, 2023, as Appl. No. 18/316,956.
Application 18/316,956 is a continuation of application No. 17/855,119, filed on Jun. 30, 2022, granted, now 11,652,158.
Application 17/855,119 is a continuation of application No. 17/176,970, filed on Feb. 16, 2021, granted, now 11,380,776, issued on Jul. 5, 2022.
Claims priority of provisional application 63/084,909, filed on Sep. 29, 2020.
Prior Publication US 2023/0282731 A1, Sep. 7, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6656 (2013.01) [H01L 21/28518 (2013.01); H01L 29/0847 (2013.01); H01L 29/41791 (2013.01); H01L 29/45 (2013.01); H01L 29/4983 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a fin comprising a channel region and a source/drain region adjacent the channel region;
a gate structure wrapping over the channel region;
a multilayer gate spacer disposed along sidewalls of the gate structure;
a source/drain feature disposed over the source/drain region; and
a multilayer contact etch stop layer (CESL) disposed along sidewalls of the multilayer gate spacer and on the source/drain feature,
wherein the multilayer gate spacer comprises a low-k dielectric layer in contact with the sidewall of the gate structure and a first silicon sublayer over the low-k dielectric layer,
wherein the multilayer CESL comprises a second silicon sublayer in contact with the sidewall of the multilayer gate spacer and a nitrogen-containing sublayer over the second silicon sublayer.