| CPC H01L 29/66553 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6681 (2013.01); H01L 29/7853 (2013.01); H01L 29/78696 (2013.01); H01L 29/0847 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate having a top surface;
a stack of channel layers over the semiconductor substrate, the stack including a first channel layer, a second channel layer over the first channel layer, and a third channel layer over the second channel layer, the first channel layer being separated from the semiconductor substrate, and the first, the second, and the third channel layers each extending in parallel to the top surface along a first direction;
a first gate portion between the first and the second channel layers, the first gate portion having a first gate thickness along a second direction perpendicular to the first direction;
a second gate portion between the second and the third channel layers, the second gate portion having a second gate thickness along the second direction;
a first inner spacer between the first and the second channel layers adjacent the first gate portion; and
a second inner spacer between the second and the third channel layers adjacent the second gate portion,
wherein the first gate thickness is greater than the second gate thickness,
wherein the first and the second gate portions have the same gate length along the first direction,
wherein the first inner spacer has a first width along the first direction, the second inner spacer has a second width along the first direction, and the first width is greater than the second width.
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7. A semiconductor device, comprising:
a substrate;
a stack of channel layers over the substrate and extending lengthwise along a first direction;
a gate structure wrapping around each of the channel layers, wherein the channel layers are separated from each other by portions of the gate structure; and
source/drain (S/D) features on sidewalls of the stack of channel layers,
a stack of inner spacers adjacent to the gate structure and in between the stack of channel layers, the stack of inner spacers separating the gate structure from the S/D features, wherein each of the inner spacers includes a first side surface facing the gate structure, a second side surface facing one of the S/D features, wherein a width of the inner spacers between the first and the second side surfaces increases along the first direction from a top surface to a bottom surface of the stack of inner spacers, wherein a maximum vertical thickness of the inner spacers increases along a second direction perpendicular to the first direction from the top surface to the bottom surface of the stack of inner spacers,
wherein a first gate portion wraps around a first one of the channel layers, a second gate portion wraps around a second one of the channel layers over the first one of the channel layers, and a third gate portion wraps around a third one of the channel layers over the second one of the channel layers.
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17. A semiconductor device, comprising:
a semiconductor substrate having a top surface;
a first source/drain feature and a second source/drain feature over the semiconductor substrate;
a first channel layer over the semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer, the first, the second, and the third channel layers each directly contacting side surfaces of the first and the second source/drain features by extending lengthwise along a first direction parallel to the top surface;
a first gate portion between the substrate and the first channel layer, a second gate portion between the first and the second channel layers, and a third gate portion between the second and the third channel layers; and
a first inner spacer adjacent to the first gate portion and between the substrate and the first channel layer, a second inner spacer adjacent to the second gate portion and between the first and the second channel layers, and a third inner spacer adjacent to the third gate portion and between the second and the third channel layers,
wherein the first, the second, and the third gate portions each has a width that is substantially the same as each other along the first direction,
wherein the first, the second, and the third gate portions each has a thickness that is different from each other along a second direction perpendicular to the first direction,
wherein the first gate portion is thicker than the second gate portion, and the second gate portion is thicker than the third gate portion.
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