US 12,148,810 B2
Semiconductor device and method
Shih-Hang Chiu, Taichung (TW); Chung-Chiang Wu, Taichung (TW); Jo-Chun Hung, Hsinchu (TW); Wei-Cheng Wang, Hsinchu (TW); Kuan-Ting Liu, Hsinchu (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 13, 2023, as Appl. No. 18/154,087.
Application 18/154,087 is a continuation of application No. 17/165,142, filed on Feb. 2, 2021, granted, now 11,594,610.
Claims priority of provisional application 63/091,969, filed on Oct. 15, 2020.
Prior Publication US 2023/0140968 A1, May 11, 2023
Int. Cl. H01L 29/49 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/4908 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28088 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a nanoFET comprising:
forming on a substrate a multi-layer stack of alternating layers of first and second semiconductor material;
removing the alternating layers of first semiconductor material and patterning the layers of second semiconductor material to form respective channel regions in the second semiconductor material separated by respective gaps, and a recess formed above a topmost channel region of the respective channel regions; and
forming a gate structure in the respective gaps and between the respective channel regions, by:
conformally depositing a gate dielectric layer on respective channel regions, and in the recess,
conformally depositing a first work function layer on the gate dielectric layer,
conformally depositing an anti-reaction layer on the first work function layer;
etching back upper portions of the anti-reaction layer and etching back upper portions of the first work function layer, such that a portion of the anti-reaction layer remains within lower part of the respective gaps and along walls of the respective channel regions, and a portion of first work function layer remains within the lower parts of the respective gaps and along walls of the respective channel regions; and
depositing a fill conductive layer to fill the respective gaps.