US 12,148,807 B2
Backside contact structures with stacked metal silicide layers for source/drain region of fin field transistors
Chia-Hung Chu, Taipei (TW); Ding-Kang Shih, New Taipei (TW); Keng-Chu Lin, Chao-Chou (TW); Pang-Yen Tsai, Jhu-bei (TW); Sung-Li Wang, Zhubei (TW); Shuen-Shin Liang, Hsinchu County (TW); Tsungyu Hung, Hsinchu (TW); and Hsu-Kai Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 9, 2021, as Appl. No. 17/371,245.
Prior Publication US 2023/0012147 A1, Jan. 12, 2023
Int. Cl. H01L 29/417 (2006.01); H01L 21/285 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/41775 (2013.01) [H01L 21/28518 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a semiconductor device on a first side of a substrate, wherein the semiconductor device comprises a source/drain (S/D) region;
etching a portion of the S/D region on a second side of the substrate to form an opening, wherein the second side is opposite to the first side; and
forming an epitaxial contact structure on the S/D region in the opening, wherein the epitaxial contact structure comprises a first portion in contact with the S/D region in the opening and a second portion on the first portion, a width of the second portion being larger than the first portion.