US 12,148,805 B2
Semiconductor structure with wraparound backside amorphous layer
Shih-Chuan Chiu, Hsinchu (TW); Huan-Chieh Su, Tianzhong Township (TW); Pei-Yu Wang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); Chun-Yuan Chen, Hsinchu (TW); Li-Zhen Yu, New Taipei (TW); Chia-Hao Chang, Hsinchu (TW); Yu-Ming Lin, Hsinchu (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,864.
Application 18/446,864 is a continuation of application No. 17/331,350, filed on May 26, 2021, granted, now 11,777,003.
Prior Publication US 2023/0387225 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 29/26 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/41733 (2013.01) [H01L 29/0665 (2013.01); H01L 29/263 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of nanostructures vertically spaced apart from each other;
an epitaxial feature coupled to one end of each of the plurality of nanostructures and having a front side and a backside;
an amorphous semiconductor layer formed around the epitaxial feature on the backside;
a first silicide layer formed over the amorphous semiconductor layer; and
a first metal contact formed over the first silicide layer.