| CPC H01L 29/402 (2013.01) [H01L 29/0649 (2013.01); H01L 29/4011 (2019.08); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 17 Claims |

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1. A driver circuit comprising:
a gate layer between a source conductor and a drain conductor, vertically separated from the source conductor by a first electrical isolation layer, and vertically separated from the drain conductor by a second electrical isolation layer;
a vertical channel intersecting the gate layer, the vertical channel including a vertical channel semiconductor material to connect vertically between the source conductor and the drain conductor, and a gate oxide between the channel semiconductor material and the gate conductor, surrounding the channel semiconductor material, wherein the gate conductor contacts the gate oxide; and
a field plate electrically coupled to the gate layer and extending from the gate layer into the second electrical isolation layer, parallel to the vertical channel, wherein the field plate has a staircase structure with at least two steps, where the field plate does not contact the gate oxide, and the staircase steps increase the vertical thickness of the field plate farther into the second isolation layer as the field plate extends farther away from the vertical channel, the field plate including a field plate conductor having a physical structure to trigger an additional electrical field peak in the vertical channel when a voltage differential exists between the source conductor and the drain conductor, and when the gate conductor is not biased, the additional electrical field peak in addition to an electrical field peak in the vertical channel due to the gate layer.
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