US 12,148,796 B2
Semiconductor device
Cheng-Pu Chiu, New Taipei (TW); Tzung-Ying Lee, Ping-Tung County (TW); Dien-Yang Lu, Kaohsiung (TW); Chun-Kai Chao, Kaohsiung (TW); and Chun-Mao Chiou, Chiayi County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Aug. 18, 2023, as Appl. No. 18/235,358.
Application 18/235,358 is a continuation of application No. 17/670,528, filed on Feb. 14, 2022, granted, now 11,764,261.
Application 17/670,528 is a continuation of application No. 17/100,963, filed on Nov. 23, 2020, granted, now 11,289,572, issued on Mar. 29, 2022.
Claims priority of application No. 202011153977.9 (CN), filed on Oct. 26, 2020.
Prior Publication US 2023/0395657 A1, Dec. 7, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 29/7851 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a logic region and a high-voltage (HV) region;
a first gate structure on the HV region;
a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, wherein the first epitaxial layer and the second epitaxial layer are not contacting each other directly under a cross-section perspective;
a first contact plug between the first epitaxial layer and the second epitaxial layer, wherein a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug; and
an interlayer dielectric (ILD) layer under the first contact plug and between the first epitaxial layer and the second epitaxial layer.