| CPC H01L 29/0649 (2013.01) [H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11831 (2013.01); H01L 2027/11892 (2013.01)] | 20 Claims |
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1. An integrated chip comprising:
a first source/drain region arranged over a substrate;
a second source/drain region arranged over the substrate;
a channel structure arranged over the substrate and between the first source/drain region and the second source/drain region;
a gate electrode arranged directly over the channel structure;
a first air spacer structure arranged on a first sidewall of the gate electrode and directly over the channel structure;
a second air spacer structure arranged on a second sidewall of the gate electrode and directly over the channel structure;
a high-k dielectric layer arranged directly between the gate electrode and the channel structure and arranged directly on outer sidewalls of the gate electrode;
a low-k spacer structure having an L-shaped profile exposed within the first air spacer structure, and further demarcating a bottom boundary and a sidewall boundary of the first air spacer structure, wherein the low-k spacer structure separates the first air spacer structure from the gate electrode;
a pair of dielectric fin structures directly between which the channel structure is arranged; and
a pair of high-k spacer structures respectively atop the pair of dielectric fin structures and directly between which the gate electrode is arranged;
wherein the first and second source/drain regions have individual sidewalls facing away from the gate electrode in a dimension, wherein the pair of dielectric fin structures have a length in the dimension exceeding a separation between the individual sidewalls, and wherein the pair of high-k spacer structures have individual widths in the dimension closer to a width of the gate electrode in the dimension than to the length.
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