	US 12,148,794 B2
	Method of manufacturing a semiconductor device and a semiconductor device
Shu Kuan, Keelung (TW); Shahaji B. More, Hsinchu (TW); Chien Lin, Hsinchu (TW); Cheng-Han Lee, New Taipei (TW); and Shih-Chieh Chang, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 29, 2022, as Appl. No. 17/853,687.
Application 17/853,687 is a continuation of application No. 16/934,887, filed on Jul. 21, 2020, granted, now 11,393,898.
Claims priority of provisional application 62/982,715, filed on Feb. 27, 2020.
Prior Publication US 2022/0328621 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 29/423 (2006.01)

CPC H01L 29/0649 (2013.01) [H01L 29/42392 (2013.01); H01L 29/0669 (2013.01); H01L 29/161 (2013.01)]

20 Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked along a stacked direction;

forming a sacrificial gate structure over the fin structure;

etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;

laterally etching the first semiconductor layers through the source/drain space; and

forming a source/drain epitaxial layer in the source/drain space,

wherein a composition of at least one of the first semiconductor layers varies, within the at least one of the first semiconductor layers, along the stacked direction,

the first semiconductor layers comprise SiGe and the second semiconductor layers comprise Si,

a Ge concentration of the first semiconductor layers decreases from a bottom one closest to a substrate to a top one of the first semiconductor layers, and

a difference of a Ge concentration between adjacent first semiconductor layers is in a range from 0.5% to 5.0%.