US 12,148,793 B2
High voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material
Min-Hwa Chi, Qingdao (CN); Min Li, Qingdao (CN); and Richard Ru-Gin Chang, Qingdao (CN)
Assigned to SiEn (QingDao) Integrated Circuits Co., Ltd., Qingdao (CN)
Filed by SiEn (QingDao) Integrated Circuits Co., Ltd., Qingdao (CN)
Filed on Nov. 20, 2023, as Appl. No. 18/514,976.
Application 18/514,976 is a division of application No. 17/352,206, filed on Jun. 18, 2021, granted, now 11,862,674.
Claims priority of application No. 202010583287.0 (CN), filed on Jun. 23, 2020.
Prior Publication US 2024/0088216 A1, Mar. 14, 2024
Int. Cl. H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 29/1095 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A high voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material, characterized by: the high voltage semiconductor device comprises:
an active area formed with the high voltage semiconductor device;
a combined junction terminal protection structure having a RESURF (Reduced Surface Field) structure, the RESURF structure comprising a first biasing field plate electrically connecting to the active area, a second biasing field plate electrically connecting to the active area and a ferroelectric material layer positioned below the first biasing field plate and in contact with the first biasing field plate, wherein the second biasing field plate is formed on the first biasing field plate and isolated with an interlayer dielectric layer, and a lateral distance between a free end of the second biasing field plate and a free end of the first biasing field plate is greater than a thickness of the interlayer dielectric layer.