US 12,148,762 B2
Array substrate and display panel
Xingfeng Ren, Beijing (CN); Mingjing Li, Beijing (CN); and Mingjian Yu, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on May 26, 2022, as Appl. No. 17/804,210.
Application 17/804,210 is a continuation of application No. 16/396,025, filed on Apr. 26, 2019, granted, now 11,380,713.
Claims priority of application No. 201811093705.7 (CN), filed on Sep. 19, 2018.
Prior Publication US 2022/0293637 A1, Sep. 15, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10K 59/131 (2023.01); H10K 59/35 (2023.01)
CPC H01L 27/124 (2013.01) [H01L 23/5221 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 27/1244 (2013.01); H10K 59/131 (2023.02); H10K 59/1315 (2023.02); H10K 59/351 (2023.02)] 17 Claims
OG exemplary drawing
 
1. An array substrate, comprising a base substrate and a first conductive layer, a first insulating layer, a second conductive layer, and a third conductive layer which are sequentially stacked on the base substrate,
wherein the first insulating layer insulates the first conductive layer from the second conductive layer, the first conductive layer comprises a first signal line extended along a first direction, the second conductive layer comprises a second signal line extended along a second direction and a first connection part which is spaced apart from the second signal line, the first direction intersecting the second direction, and the third conductive layer comprises a second connection part;
the first connection part is electrically connected with the first signal line through a first via hole in the first insulating layer;
the second connection part is respectively electrically connected with the second signal line and the first connection part to electrically connect the first signal line and the second signal line;
an orthographic projection of the first signal line on the base substrate is at least partially overlapped with an orthographic projection of the second connection part on the base substrate and an orthographic projection of the first connection part on the base substrate is at least partially overlapped with the orthographic projection of the second connection part on the base substrate;
an orthographic projection of the second signal line on the base substrate is intersected with the orthographic projection of the first signal line on the base substrate;
the first connection part is in contact with an upper surface of the first insulating layer;
the first insulating layer does not comprise a via hole which is overlapped with the second signal line in a direction perpendicular to the base substrate;
the first connection part comprises two sub-connection parts, and the two sub-connection parts are respectively at two sides of the second signal line; and
the second connection part is at least partially overlapped with each of the two sub-connection parts in the direction perpendicular to the base substrate and is electrically connected with each of the two sub-connection parts;
the array substrate further comprises a plurality of sub-pixels arranged in a plurality of rows along the first direction and a plurality of columns along the second direction;
each of the plurality of sub-pixels comprises a thin film transistor, and the first signal line and the second signal line are electrically connected with a source electrode or a drain electrode of the thin film transistor; and
each sub-pixel further comprises a pixel electrode, and the third conductive layer further comprises the pixel electrode.