US 12,148,761 B2
Display device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Apr. 5, 2021, as Appl. No. 17/221,896.
Application 14/072,878 is a division of application No. 13/117,658, filed on May 27, 2011, granted, now 8,598,591, issued on Dec. 3, 2013.
Application 13/117,658 is a division of application No. 12/694,514, filed on Jan. 27, 2010, granted, now 7,964,876, issued on Jun. 21, 2011.
Application 12/694,514 is a division of application No. 11/863,913, filed on Sep. 28, 2007, granted, now 7,687,808, issued on Mar. 30, 2010.
Application 17/221,896 is a continuation of application No. 16/728,254, filed on Dec. 27, 2019, granted, now 10,978,497.
Application 16/728,254 is a continuation of application No. 16/429,199, filed on Jun. 3, 2019, granted, now 10,685,987, issued on Jun. 16, 2020.
Application 16/429,199 is a continuation of application No. 16/190,249, filed on Nov. 14, 2018, granted, now 10,553,618, issued on Feb. 4, 2020.
Application 16/190,249 is a continuation of application No. 15/899,472, filed on Feb. 20, 2018, granted, now 10,134,775, issued on Nov. 20, 2018.
Application 15/899,472 is a continuation of application No. 15/427,103, filed on Feb. 8, 2017, granted, now 10,062,716, issued on Aug. 28, 2018.
Application 15/427,103 is a continuation of application No. 15/000,096, filed on Jan. 19, 2016, granted, now 9,583,513, issued on Feb. 28, 2017.
Application 15/000,096 is a continuation of application No. 14/072,878, filed on Nov. 6, 2013, granted, now 9,245,891, issued on Jan. 26, 2016.
Claims priority of application No. 2006-269689 (JP), filed on Sep. 29, 2006.
Prior Publication US 2021/0320129 A1, Oct. 14, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H01H 71/02 (2006.01); H01H 71/10 (2006.01); H01L 27/105 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); G02F 1/1343 (2006.01); G02F 1/1345 (2006.01); H01L 27/13 (2006.01); H01L 29/423 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H01L 27/124 (2013.01) [G02F 1/133345 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); H01H 71/02 (2013.01); H01H 71/10 (2013.01); H01L 27/105 (2013.01); H01L 27/12 (2013.01); H01L 27/1214 (2013.01); H01L 27/1222 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 29/78663 (2013.01); H01L 29/78678 (2013.01); G02F 1/134309 (2013.01); G02F 1/13454 (2013.01); G02F 1/13624 (2013.01); G02F 2202/103 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0417 (2013.01); G09G 2300/0426 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); G09G 2330/023 (2013.01); H01L 27/13 (2013.01); H01L 29/42384 (2013.01); H01L 29/78696 (2013.01); H10K 59/1213 (2023.02); H10K 59/131 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A display device comprising:
a scan line driver circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein a gate of the fourth transistor is electrically connected to a gate of the first transistor,
wherein the fourth wiring is supplied with a first clock signal, and
wherein the scan line driver circuit is configured to output a scan signal to the first wiring.