US 12,148,754 B2
Integrated circuit structure with hybrid cell design
Kam-Tou Sio, Hsinchu County (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Nov. 28, 2022, as Appl. No. 18/070,303.
Application 18/070,303 is a division of application No. 16/900,768, filed on Jun. 12, 2020, granted, now 11,515,308.
Prior Publication US 2023/0093380 A1, Mar. 23, 2023
Int. Cl. H01L 27/092 (2006.01); G06F 30/392 (2020.01)
CPC H01L 27/0924 (2013.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an silicon germanium (SiGe) structure over a first region of a non-SiGe substrate;
patterning the SiGe structure into a plurality of SiGe fins;
patterning a second region of the non-SiGe substrate into a plurality of non-SiGe fins;
performing an etching process to break a first one of the plurality of non-SiGe fins into a plurality of non-SiGe sub-fins, wherein the plurality of SiGe fins remain intact in the etching process;
forming n-type transistors on the plurality of non-SiGe sub-fins; and
forming p-type transistors on the plurality of SiGe fins.