US 12,148,752 B2
High voltage transistor structures
Meng-Han Lin, Hsinchu (TW); Wen-Tuo Huang, Tainan (TW); and Yong-Shiuan Tsair, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/815,180.
Application 17/815,180 is a division of application No. 16/657,396, filed on Oct. 18, 2019, granted, now 11,942,475.
Prior Publication US 2022/0406662 A1, Dec. 22, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/28052 (2013.01); H01L 21/823431 (2013.01); H01L 21/823443 (2013.01); H01L 21/823456 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/4933 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
depositing a silicon oxide layer on a first region of a semiconductor substrate;
depositing a high-k dielectric layer on a second region of the semiconductor substrate, wherein the high-k dielectric layer is thinner than the silicon oxide layer;
depositing a polysilicon layer on the silicon oxide layer and the high-k dielectric layer;
patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, wherein the first polysilicon gate electrode structure has a length longer than that of the second polysilicon gate electrode structure and narrower than that of the silicon oxide layer;
forming a first spacer on sidewalls of the first polysilicon gate electrode structure so that outer sidewalls of the first spacer are aligned to sidewalls of the silicon oxide layer;
forming a second spacer on sidewalls of the second polysilicon gate electrode structure and the high-k dielectric layer; and
replacing the second polysilicon gate electrode structure with a metal gate electrode structure.