US 12,148,751 B2
Use of a placeholder for backside contact formation for transistor arrangements
Andy Chih-Hung Wei, Yamhill, OR (US); Anand S. Murthy, Portland, OR (US); Mauro J. Kobrinsky, Portland, OR (US); and Guillaume Bouche, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 30, 2020, as Appl. No. 17/084,977.
Prior Publication US 2022/0139911 A1, May 5, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 23/5226 (2013.01); H01L 29/0665 (2013.01); H01L 29/41791 (2013.01); H01L 29/6681 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transistor arrangement, comprising:
a backside layer comprising a dielectric material;
an electrically conductive line;
a nanoribbon of a semiconductor material, wherein a longitudinal axis of the nanoribbon is substantially parallel to the backside layer, and wherein the backside layer is between the nanoribbon and the electrically conductive line;
a transistor that includes:
a channel portion that includes a portion of the semiconductor material of the nanoribbon, a gate stack, at least partially wrapping around the channel portion, and a first region and a second region in the nanoribbon, on either side of the channel portion, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor; and
a backside contact that includes a via that extends through the backside layer, the via having a first portion that has a first end directly electrically connected with the electrically conductive line, and further having a second portion that has a second end directly electrically connected with the first region, wherein a dimension of the first region in a direction of the longitudinal axis of the nanoribbon and in a middle of the nanoribbon is smaller than a dimension of the first portion of the via in the direction of the longitudinal axis of the nanoribbon, and wherein a distance between the first region and the electrically conductive line is smaller than a distance between the second region and the electrically conductive line.
 
16. A transistor arrangement, comprising:
a backside layer comprising a dielectric material;
an electrically conductive line;
a nanoribbon of a semiconductor material, wherein a longitudinal axis of the nanoribbon is substantially parallel to the backside layer, and wherein the backside layer is between the nanoribbon and the electrically conductive line;
a transistor that includes: a channel portion that includes a portion of the semiconductor material of the nanoribbon, a gate stack, at least partially wrapping around the channel portion, and a first region and a second region in the nanoribbon, on eitherside of the channel portion, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor; and
a via extending through the backside layer, the via having a first portion that has a first end directly electrically connected with the electrically conductive line, and further having a second portion that has a second end directly electrically connected with the first region,
wherein a dimension of the first region in a direction of the longitudinal axis of the nanoribbon and in a middle of the nanoribbon is smaller than a dimension of the first portion of the via in the direction of the longitudinal axis of the nanoribbon, a dimension of the second portion of the via in the direction of the longitudinal axis of the nanoribbon is smaller than the dimension of the first portion of the via in the direction of the longitudinal axis of the nanoribbon, a portion of the second portion of the via has a subportion, the subportion is closer to the first region than a remainder of the second portion of the via, and the first region extends into the subportion.
 
18. A transistor arrangement, comprising:
a backside layer comprising a first dielectric material; an electrically conductive line;
a nanoribbon of a semiconductor material, wherein a longitudinal axis of the nanoribbon is substantially parallel to the backside layer, and wherein the backside layer is between the nanoribbon and the electrically conductive line;
a transistor that includes:
a channel portion that includes a portion of the semiconductor material of the nanoribbon, a gate stack, at least partially wrapping around the channel portion, and a first region and a second region in the nanoribbon, on either side of the channel portion, wherein one of the first region and the second region is a source region of the transistor and another one of the first region and the second region is a drain region of the transistor;
a via extending through the backside layer, the via comprising:
a first portion that has a first end directly electrically connected with the electrically conductive line, a second portion that has a second end directly electrically connected with the first region, and a subportion within the second portion, wherein the subportion is closer to the first region than a remainder of the second portion of the via, and wherein the first region extends into the subportion; and
a second dielectric material, wherein a first portion of the second dielectric material is on a sidewall of the via, and a second portion of the second dielectric material is between the second region and the first dielectric material, wherein a distance between the electrically conductive line and first region extending into the subportion is smaller than a distance between the electrically conductive line and the second portion of the second dielectric material.