US 12,148,750 B2
Work function design to increase density of nanosheet devices
Mao-Lin Huang, Hsinchu (TW); Chih-Hao Wang, Baoshan Township (TW); Kuo-Cheng Chiang, Zhubei (TW); Jia-Ni Yu, New Taipei (TW); Lung-Kun Chu, New Taipei (TW); and Chung-Wei Hsu, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 16, 2023, as Appl. No. 18/511,064.
Application 18/511,064 is a continuation of application No. 17/676,403, filed on Feb. 21, 2022, granted, now 11,862,633.
Application 17/676,403 is a continuation of application No. 16/874,907, filed on May 15, 2020, granted, now 11,257,815, issued on Feb. 22, 2022.
Claims priority of provisional application 62/928,525, filed on Oct. 31, 2019.
Prior Publication US 2024/0096880 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/02603 (2013.01); H01L 21/823412 (2013.01); H01L 21/82345 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first channel structure within a first transistor device;
a first gate electrode layer wrapping around the first channel structure;
a second channel structure within a second transistor device;
a second gate electrode layer wrapping around the second channel structure, wherein the second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer;
a third channel structure within a third transistor device; and
a third gate electrode layer wrapping around the third channel structure, wherein the third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.