US 12,148,749 B2
Semiconductor device and method for fabricating the same
Cheol Kim, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 15, 2021, as Appl. No. 17/502,554.
Claims priority of application No. 10-2021-0033849 (KR), filed on Mar. 16, 2021.
Prior Publication US 2022/0302109 A1, Sep. 22, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/76229 (2013.01); H01L 21/823481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first active pattern which extends lengthwise in a first direction on the substrate, and includes a first side wall and a second side wall opposite to the first side wall;
a second active pattern which is spaced apart from the first active pattern in the first direction, extends lengthwise in the first direction, and includes a first side wall and a second side wall opposite to the first side wall;
a field insulation layer which surrounds side walls of each of the first and second active patterns on the substrate;
a first dam which is disposed between the first active pattern and the second active pattern, and has a lower surface at a vertical level lower than that of an upper surface of the field insulation layer;
a second dam which is spaced apart from the first side wall of the first active pattern in a second direction different from the first direction, and has a lower surface at a vertical level lower than that of the upper surface of the field insulation layer;
a first gate electrode which is disposed on the first dam between the first active pattern and the second active pattern, and extends lengthwise in the second direction;
a second gate electrode which is spaced apart from the first gate electrode in the first direction and extends lengthwise in the second direction on the first active pattern; and
a first gate cut which is spaced apart from each of the first side wall of the first active pattern and the first side wall of the second active pattern in the second direction, extends lengthwise in the first direction on the first dam, and intersects each of the first and second gate electrodes,
wherein an uppermost surface of the first dam is at a vertical level higher than vertical levels of uppermost surfaces of the first and second active patterns.