US 12,148,747 B2
Gallium nitride (GAN) three-dimensional integrated circuit technology
Han Wui Then, Portland, OR (US); Marko Radosavljevic, Portland, OR (US); Pratik Koirala, Portland, OR (US); Nicole K. Thomas, Portland, OR (US); Paul B. Fischer, Portland, OR (US); Adel A. Elsherbini, Chandler, AZ (US); Tushar Talukdar, Wilsonville, OR (US); Johanna M. Swan, Scottsdale, AZ (US); Wilfred Gomes, Portland, OR (US); Robert S. Chau, Beaverton, OR (US); and Beomseok Choi, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,513.
Prior Publication US 2022/0102339 A1, Mar. 31, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 21/765 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0605 (2013.01) [H01L 21/765 (2013.01); H01L 23/481 (2013.01); H01L 23/49844 (2013.01); H01L 23/642 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 27/0922 (2013.01); H01L 29/0673 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/402 (2013.01); H01L 29/42392 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/78696 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/13064 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19103 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a first integrated circuit (IC) die coupled to the package substrate, the first IC die comprising a GaN device layer and a Si-based CMOS layer, wherein the package substrate is a ceramic package substrate or an organic package substrate;
a plurality of interconnects coupled to and extending from the package substrate; and
a second IC die over and coupled to the first IC die and to the plurality of interconnects, wherein the second IC die is coupled to the first IC die by through structure vias of the first IC die.