US 12,148,745 B2
Integrated hybrid standard cell structure with gate-all-around device
Chih-Hao Wang, Hsinchu (TW); Shang-Wen Chang, Hsinchu County (TW); and Min Cao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/355,960.
Application 18/355,960 is a continuation of application No. 17/385,119, filed on Jul. 26, 2021, granted, now 11,764,203.
Application 17/385,119 is a continuation of application No. 16/727,731, filed on Dec. 26, 2019, granted, now 11,075,195, issued on Jul. 27, 2021.
Prior Publication US 2023/0369308 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/02 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G06F 30/392 (2020.01)
CPC H01L 27/0207 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first standard cell spanning a first dimension L1 along a first direction from a first cell edge to a second cell edge and spanning a second dimension L2 from a third cell edge to a fourth cell edge along a second direction being orthogonal to the first direction, wherein the first standard cell includes a first active region and a second active region oriented along the second direction, and wherein the first active region and the second active region are spaced away with a first spacing S1 therebetween;
a second standard cell spanning a third dimension L3 along the first direction from a fifth cell edge to a sixth cell edge and spanning a fourth dimension L4 from a seventh cell edge to an eighth cell edge along the second direction, wherein the second standard cell includes a third active region and a fourth active region spanning from the seventh cell edge to the eighth cell edge along the second direction, wherein the third active region and the fourth active region are spaced away with a second spacing S2 therebetween, wherein S2 is equal to S1, wherein L3 is less than L1 and L4 is equal to L2, and wherein the second standard cell is disposed such that the fifth cell edge is overlapped with the second cell edge; and
a plurality of gate stacks oriented along the first direction and continuously extend from the sixth cell edge of the second standard cell to the first cell edge of the first standard cell.