US 12,148,736 B2
Three-dimensional bonding scheme and associated systems and methods
Kelvin Tan Aik Boo, Singapore (SG); Hong Wan Ng, Singapore (SG); Seng Kim Ye, Singapore (SG); and Chin Hui Chong, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 3, 2022, as Appl. No. 17/592,065.
Claims priority of provisional application 63/238,098, filed on Aug. 27, 2021.
Prior Publication US 2023/0069476 A1, Mar. 2, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 25/50 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a package substrate;
a stack of semiconductor dies carried by the package substrate, the stack of semiconductor dies including a first die carried by the package substrate and a second die carried by the first die; and
an interconnect module carried by the package substrate adjacent the stack of semiconductor dies, the interconnect module having at least a first tier and a second tier, wherein:
the first tier is carried by and electrically coupled to the package substrate, wherein the first tier includes a first plurality of bond pads;
the second tier has a first end carried by and electrically coupled to the first tier and a second end opposite the first end, wherein the second tier includes a second plurality of bond pads, wherein each bond pad in the first plurality of bond pads is electrically connected to two corresponding bond pads in the second plurality of bond pads, and
the second die is electrically coupled to at least a subset of the second plurality of bond pads.
 
10. A semiconductor device package, comprising:
a package substrate;
a stack of semiconductor dies carried by the package substrate, the stack of semiconductor dies comprising:
a first sub-stack carried by the package substrate at a first elevation, the first sub-stack including a lowermost die attached to the package substrate and an uppermost die above the lowermost die, wherein each die in the first sub-stack is electrically connected to the lowermost die; and
a second sub-stack carried by the first sub-stack at a second elevation, the second sub-stack including an intermediary die carried by the uppermost die in the first sub-stack, wherein each die in the second sub-stack is electrically connected to the intermediary die; and
a three-dimensional interconnect module electrically connected to the package substrate, the three-dimensional interconnect module including a first plurality of bond pads at the first elevation and a second plurality of bond pads at the second elevation, wherein the first plurality of bond pads is electrically connected to the package substrate, and wherein the intermediary die in the second sub-stack is electrically connected to the second plurality of bond pads.
 
15. A semiconductor device, comprising:
a package substrate;
a stack of semiconductor dies carried by the package substrate, the stack of semiconductor dies comprising a first sub-stack of two or more dies carried by the package substrate and a second sub-stack of two or more carried by the first sub-stack; and
an interconnect module electrically connected to the package substrate, the interconnect module comprising:
a first tier having a first plurality of bond pads, wherein the first plurality of bond pads is electrically coupled to the package substrate by first wirebonds; and
a second tier electrically coupled to the first tier, the second tier having a second plurality of bond pads, wherein the second sub-stack is electrically coupled to the second plurality of bond pads by second wirebonds.