US 12,148,735 B2
Memory device and manufacturing method thereof
Ching-Yu Huang, Hsinchu (TW); Han-Ping Pu, Taichung (TW); Ming-Kai Liu, Hsinchu (TW); Ting-Chu Ko, Hsinchu (TW); Yung-Ping Chiang, Hsinchu County (TW); Chang-Wen Huang, Hsinchu (TW); and Yu-Sheng Hsieh, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 19, 2022, as Appl. No. 17/723,484.
Application 17/723,484 is a division of application No. 16/924,192, filed on Jul. 9, 2020, granted, now 11,335,666.
Prior Publication US 2022/0246578 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 23/3731 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/214 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming first redistribution patterns in a first dielectric layer;
forming second redistribution patterns electrically connected with the first redistribution patterns on the first dielectric layer with a first material;
forming a thermally conductive layer electrically isolated from the first redistribution patterns and the second redistribution patterns over the first dielectric layer with a second material different form the first material; and
forming a second dielectric layer over the first dielectric layer, wherein the second redistribution patterns and the thermally conductive layer are embedded in the second dielectric layer.